Micron drops 4F2 DRAM, extends 6F2 and bets on 3D DRAM

Micron changed direction on its memory map. The company said the 4F2 memory cell will not enter the plan despite twenty years of work. The word came at a technology session on October 21, 2026 from Scott DeBoer, who leads products and technology. The reason is plain: density follows capacitor spacing rather than cell drawing alone, while 4F2 adds steps and cost. The TrendForce write-up says the firm will stretch the current 6F2 layout and head toward 3D memory over time. That is a patient hardware choice rather than a sharp break.

Why capacitor spacing decides

Think of a memory cell like a small bowl. Even with a narrower bowl, if the spoon inside stays the same size, the shelf holds no more bowls. In DRAM the spoon is the capacitor that holds charge. Moving from a 6F2 drawing to a 4F2 drawing saves area on paper, yet tight capacitors raise leak and factory pain. The note on bits-chips.com makes the same point: added complexity and cost wipe out the density gain. So Micron keeps the same bowl and arranges it better across coming nodes. That fits a hardware style of fewer steps and steady gains.

The current node is already in volume. The 1-gamma memory node carries more than half of shipped bits and feeds server plus mobile device memory. It uses extreme ultraviolet print and a new gate material, which lift efficiency at the same footprint. The Micron page on micron.com describes it as a sixth-generation 10nm-class node, and the investor notice confirms the session date. So the map stands on a working memory generation rather than a promise. For device buyers that means near-term supply comes from this node.

1-delta and DDR6 targets

The next stop is 1-delta. That memory node should reach volume in the second half of 2027 with a mid-20s percent density lift. The build site named is Boise. DDR6 server memory will feed from it and aims at twice the bandwidth of DDR5. LPDDR6 targets about 35 percent better power efficiency, with larger gains at some densities. The Wccftech outline carries these figures from the session. Picture a wider pipe: with double width, a server rack moves double the data in the same time. This is the most concrete hardware promise in the deck.

There is also a vertical stack path. HBM4 is already in volume at about 2.8 TB per stack. Work continues on HBM5 and vertically stacked memory. In the vertical design, memory sits directly on the logic chip, so the path shortens and bandwidth per watt rises. The TweakTown report calls this layout a new favorite for server racks and flags heat control as an open risk. Stacked layers trap warmth, so cooling plus hybrid bonding belong to the same task. When memory moves into the same building as logic, the elevator gets shorter, yet ventilation must be rebuilt.

Later nodes are already sketched. The 1-epsilon node will use wafer bonding for more density, while 1-zeta and 1-eta will test high-aperture ultraviolet print and fresh materials. Stacked 3D memory sits between zeta and eta on the chart, with work running beside planar memory. Timing depends on cost, factory pain, and device demand. The investor notice says the session opened this long view for the first time. In other words the firm bets on small compounding gains per node rather than one jump. That is marathon work on the chip side.

Why CXMT walks another road

The Chinese maker CXMT takes the opposite bet. At a Shanghai meeting on October 10 it promised a 4F2 DDR5 server module before year end. The part is a registered stick for server racks. The TomsHardware record says vertical surround transistors cut cell area by about a third on paper, with no speed or capacity figures shared. So there is a promise without figures. The contrast matters, because Micron shelved as costly the same road CXMT now brings to product. Two hardware kitchens will test a similar dish with different recipes.

The NAND side has a firm date too. The G11 flash node should ramp in the second half of 2027 with more than 400 layers and wafer-on-wafer bonding. The goal is twice the density of G9, about 1.5 times the input-output speed, and lower move energy. The TrendForce record carries these figures from the session, and the TweakTown report gives the same range. Phone and laptop storage chips feed from this side. If DRAM is about work in motion, NAND is about keeping, and both open room on the device side.

Across the whole picture three items stay on watch. First the 1-delta promise: volume plus mid-20s density in the second half of 2027. Second whether bonding and heat tasks clear for vertically stacked memory. Third whether CXMT ships its first 4F2 server part by year end. DDR6 has no firm date and 3D memory carries a cost condition. So read this story as a middle gate rather than a final. On the memory side the calendar plus shelf price will pick the winner, not the slides.